Engineering and Computer Science Faculty Publications
A Fast, Low-Power Logarithm Approximation with CMOS VLSI Implementation
Document Type
Conference Proceeding
Publication Date
1999
Journal Title
Proceedings of the Midwest Symposium on Circuits and Systems
Abstract
A new technique and CMOS VLSI implementation for computing approximate logarithms (base 2, and 10) for binary integers is presented. The approximation is performed using only combinational logic and requires no multiplications. Additionally, as implemented a ROM of only N*log2(N) bits is used to convert N bit integers. The maximum error of the approximation is 1.5% when the input value is 3, and decays exponentially to less than 0.5% for input values greater than 25.
Recommended Citation
SanGregory, Samuel L.; Brothers, Charles; Gallagher, David; and Siferd, Raymond, "A Fast, Low-Power Logarithm Approximation with CMOS VLSI Implementation" (1999). Engineering and Computer Science Faculty Publications. 21.
https://digitalcommons.cedarville.edu/engineering_and_computer_science_publications/21
